RX CH0 interrupt raw register
| IN_DONE_CH0_INT_RAW | The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 0. |
| IN_SUC_EOF_CH0_INT_RAW | The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. |
| IN_ERR_EOF_CH0_INT_RAW | The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected |
| IN_DSCR_ERR_CH0_INT_RAW | The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. |
| INFIFO_OVF_L1_CH0_INT_RAW | The raw interrupt bit turns to high level when fifo of Rx channel is overflow. |
| INFIFO_UDF_L1_CH0_INT_RAW | The raw interrupt bit turns to high level when fifo of Rx channel is underflow. |
| INFIFO_OVF_L2_CH0_INT_RAW | The raw interrupt bit turns to high level when fifo of Rx channel is overflow. |
| INFIFO_UDF_L2_CH0_INT_RAW | The raw interrupt bit turns to high level when fifo of Rx channel is underflow. |
| IN_DSCR_EMPTY_CH0_INT_RAW | The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. |
| IN_DSCR_TASK_OVF_CH0_INT_RAW | The raw interrupt bit turns to high level when dscr ready task fifo is overflow. |